UGC NET Computer Science Computer System Architecture Previous Year Questions (PYQs)

All 40 Computer System Architecture PYQs

Ordered newest exam first. Each question links back to the full paper it came from.

1. Question 1

   UGC NET January 2025

   Give the correct order of the instruction cycle:

   A. Read the effective address
   B. Fetch the instruction
   C. Execute the instruction
   D. Decode the instruction

   1. AA, B, C, D
   2. BB, D, A, C
   3. CB, A, D, C
   4. DA, B, D, C

   Answer: (B) B, D, A, C

   Explanation

   A processor fetches an instruction, decodes it, obtains the effective address where needed, and executes it. Therefore B, D, A, C is correct. The correct option follows from the stated definition or calculation; the other options omit a necessary condition or describe a different concept.

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2. Question 2

   UGC NET January 2025

   Which of the following do not represent memory-reference instructions?

   1. AB and C only
   2. BB and D only
   3. CA and D only
   4. DA and E only

   Answer: (B) B and D only

   Explanation

   In the basic computer instruction format, the opcode determines whether an instruction refers to memory; the source combinations labelled B and D correspond to non-memory-reference cases. The correct option follows from the stated definition or calculation; the other options omit a necessary condition or describe a different concept.

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3. Question 3

   UGC NET January 2025

   Match List-I with List-II.

   List-I	List-II
   A. (11011)₂ B. Complements C. Parity bits D. Variable-length instruction	I. Error-detection code II. CISC III. Negative number IV. (33)₁₆

   1. AA-IV, B-I, C-III, D-II
   2. BA-IV, B-III, C-I, D-II
   3. CA-IV, B-II, C-III, D-I
   4. DA-I, B-IV, C-II, D-III

   Answer: (B) A-IV, B-III, C-I, D-II

   Explanation

   (11011)₂ equals (33)₁₆; complements represent negative numbers; parity bits are error-detection codes; and variable-length instructions are characteristic of CISC. The correct option follows from the stated definition or calculation; the other options omit a necessary condition or describe a different concept.

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4. Question 4

   UGC NET January 2025

   A pipeline multiplier uses two carry-save adders (CSAs) and a carry-propagate adder (CPA). Arrange the following stages in the proper order.

   A. Two CSAs merge four numbers into two numbers.
   B. A CPA adds two numbers.
   C. Two levels of four CSAs are used.
   D. Eight partial products are generated.

   1. AA, C, B, D
   2. BD, C, A, B
   3. CB, D, C, A
   4. DA, C, D, B

   Answer: (B) D, C, A, B

   Explanation

   A multiplier first generates partial products, reduces them through carry-save-adder levels, compresses the final four values to two, and uses a carry-propagate adder last. Hence D, C, A, B.

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5. Question 5

   UGC NET January 2025

   Which of the following are not data-manipulation instructions?

   A. Call
   B. Load
   C. And
   D. Increment
   E. Shift

   1. AC and E only
   2. BA and B only
   3. CD and E only
   4. DA and C only

   Answer: (B) A and B only

   Explanation

   The official answer key selects Call and Load. The item uses “data-manipulation instructions” in its particular instruction-set classification, distinguishing control/transfer and load operations from arithmetic/logical manipulation.

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6. Question 6

   UGC NET January 2025

   Arrange the following in increasing order of access time.

   A. Solid-state drive
   B. Optical disks
   C. DRAM
   D. SRAM
   E. Registers

   1. AD, C, A, B, E
   2. BB, D, C, A, E
   3. CA, E, B, D, C
   4. DE, D, C, A, B

   Answer: (D) E, D, C, A, B

   Explanation

   Registers are fastest, followed by SRAM, DRAM, SSD and optical disk. Thus increasing access time is E, D, C, A, B. The correct option follows from the stated definition or calculation; the other options omit a necessary condition or describe a different concept.

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7. Question 7

   UGC NET January 2025

   Which table for a dynamic pipeline becomes more interesting when a nonlinear pattern follows?

   1. AReservation table
   2. BConfusion table
   3. CInverted table
   4. DGreedy table

   Answer: (A) Reservation table

   Explanation

   A reservation table records stage use over time. It is the standard representation for analysing collision constraints and nonlinear patterns in dynamic pipelines. The correct option follows from the stated definition or calculation; the other options omit a necessary condition or describe a different concept.

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8. Question 8

   UGC NET January 2025

   Which is often needed to evaluate cache performance?

   1. AHit ratio
   2. BLatency
   3. CCache traces
   4. DTransfer rate

   Answer: (A) Hit ratio

   Explanation

   The hit ratio is the basic measure of how often cache accesses are satisfied by the cache rather than a slower lower memory level. The correct option follows from the stated definition or calculation; the other options omit a necessary condition or describe a different concept.

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9. Question 9

   UGC NET August 2024

   Consider the following relations on {1, 2, 3, 4}. Which of the following relations are reflexive?

   A. R₁ = {(1,1),(1,2),(2,1),(2,2),(3,4),(4,1),(4,4)}
   B. R₂ = {(1,1),(1,2),(2,1)}
   C. R₃ = {(1,1),(1,2),(1,4),(2,1),(2,2),(3,3),(4,1),(4,4)}
   D. R₄ = {(2,1),(3,1),(3,2),(4,1),(4,2),(4,3)}
   E. R₅ = {(1,1),(1,2),(1,3),(1,4),(2,2),(2,3),(2,4),(3,3),(3,4),(4,4)}

   1. A(A), (B) and (C) Only
   2. B(A), (D) and (E) Only
   3. C(D) and (E) Only
   4. D(C) and (E) Only

   Answer: (D) (C) and (E) Only

   Explanation

   A relation on {1, 2, 3, 4} is reflexive only if it contains all four self-pairs (1,1), (2,2), (3,3) and (4,4). R₁ omits (3,3); R₂ omits (2,2), (3,3) and (4,4); R₄ contains no self-pair at all. R₃ and R₅ each contain all four, so only (C) and (E) are reflexive — option D.

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10. Question 10

    UGC NET August 2024

    Match List-I with List-II.

    List-I (IP Address)	List-II (Class)
    (A) 10.20.30.40	(I) Class E
    (B) 210.20.30.3	(II) Class B
    (C) 180.30.100.10	(III) Class A
    (D) 252.5.15.11	(IV) Class C

    1. A(A)-(II), (B)-(III), (C)-(I), (D)-(IV)
    2. B(A)-(I), (B)-(IV), (C)-(II), (D)-(III)
    3. C(A)-(I), (B)-(II), (C)-(IV), (D)-(III)
    4. D(A)-(III), (B)-(IV), (C)-(II), (D)-(I)

    Answer: (D) (A)-(III), (B)-(IV), (C)-(II), (D)-(I)

    Explanation

    The first octet fixes the class. 10 falls in 1-126, so 10.20.30.40 is Class A and (A)-(III). 210 falls in 192-223, so 210.20.30.3 is Class C and (B)-(IV). 180 falls in 128-191, so 180.30.100.10 is Class B and (C)-(II). 252 falls in 240-255, so 252.5.15.11 is Class E and (D)-(I). Option D is correct.

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11. Question 11

    UGC NET August 2024

    Find the correct sequence of the storage devices
    in descending order based on their access time.
    A. Registers
    B. Magnetic Disk
    C. Magnetic Tapes
    D. Main memory
    E. Optical Disk

    1. A(B), (A), (D), (C), (E)
    2. B(B), (A), (E), (D), (C)
    3. C(C), (B), (A), (E), (D)
    4. D(C), (E), (B), (D), (A)

    Answer: (D) (C), (E), (B), (D), (A)

    Explanation

    Descending access time means slowest first: magnetic tape (seconds), then optical disk, then magnetic disk (milliseconds), then main memory (nanoseconds), and finally registers, which are fastest. That is (C), (E), (B), (D), (A) — option D.

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12. Question 12

    UGC NET August 2024

    A CPU has a 5-stage pipeline with the following
    stages Fetch (F), Decode (D), Execute (E), Memory
    (M) and Write-back (W). Each stage takes one
    clock cycle to complete. Assume there are no
    pipeline stalls and the pipeline is initially empty.
    How many clock cycles are required to complete
    the execution of 10 instructions?

    1. A10
    2. B14
    3. C15
    4. D19

    Answer: (B) 14

    Explanation

    A k-stage pipeline completes n instructions in k + n − 1 cycles once it has been filled. With k = 5 and n = 10 that is 5 + 10 − 1 = 14 cycles, so option B is correct.

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13. Question 13

    UGC NET August 2024

    Consider the following, where p and q are two statements.

    A. ¬(p ∧ q) ≡ ¬p ∨ ¬q
    B. ¬(p ∨ q) ≡ ¬p ∧ ¬q
    C. p ∧ ¬p ≡ T
    D. ¬(p ⇒ q) ≡ p ∧ ¬q
    E. p ∨ q ≡ ¬p ∨ ¬q

    1. A(A), (B) and (D) only
    2. B(A), (C) and (D) only
    3. C(C), (D) and (E) only
    4. D(A), (B) and (C) only

    Answer: (A) (A), (B) and (D) only

    Explanation

    By De Morgan’s laws ¬(p ∧ q) ≡ ¬p ∨ ¬q and ¬(p ∨ q) ≡ ¬p ∧ ¬q, so (A) and (B) hold. For (D), p ⇒ q is ¬p ∨ q, so ¬(p ⇒ q) ≡ ¬(¬p ∨ q) ≡ p ∧ ¬q — also true. (C) fails because p ∧ ¬p is a contradiction, not a tautology, and (E) fails on the row p = q = T. Only (A), (B) and (D) — option A.

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14. Question 14

    UGC NET August 2024

    Match List-I with List-II.

    List-I (Counter)	List-II (uses/working)
    (A) N-bit Ring Counter	(I) Uses universal clock
    (B) Synchronous Counter	(II) Counts exactly N states
    (C) Asynchronous Counter	(III) Counts 0 to 9
    (D) Decimal Counter	(IV) Main clock is applied to first flip-flop only

    1. A(A)-(II), (B)-(IV), (C)-(I), (D)-(III)
    2. B(A)-(IV), (B)-(II), (C)-(III), (D)-(I)
    3. C(A)-(II), (B)-(I), (C)-(IV), (D)-(III)
    4. D(A)-(IV), (B)-(I), (C)-(II), (D)-(III)

    Answer: (C) (A)-(II), (B)-(I), (C)-(IV), (D)-(III)

    Explanation

    An N-bit ring counter cycles through exactly N states, so (A)-(II). A synchronous counter clocks every flip-flop from one common clock, giving (B)-(I). In an asynchronous (ripple) counter only the first flip-flop sees the main clock, so (C)-(IV). A decimal counter counts 0 to 9, so (D)-(III). Option C is correct.

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15. Question 15

    UGC NET August 2024

    Consider the following statement regarding
    special purpose registers.
    A. Program Counter (PC) keeps the track of next
    instruction executed
    B. Instruction register holds the address of first
    instruction to be executed
    C. Accumulator holds the output of ALU
    D. Program Counter ( PC ) keeps the track of
    only first instruction of the program

    1. A(A) and (C) Only
    2. B(A) and (D) Only
    3. C(B) and (D) Only
    4. D(A), (B) and (C) Only

    Answer: (A) (A) and (C) Only

    Explanation

    (A) is true — the program counter holds the address of the next instruction to be executed. (C) is true — the accumulator holds the ALU’s result. (B) is false: the instruction register holds the instruction currently being executed, not an address. (D) is false: the PC tracks the next instruction throughout execution, not only the first. Only (A) and (C) — option A.

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16. Question 16

    UGC NET August 2024

    A multi processor system with 16 processors is
    used to execute a parallelizable task. If the serial
    portion of the task takes 200 clock cycles and
    the parallel portion take 800 clock cycles. When
    all 16 processor are used how many total clock
    cycles are required to complete the task ?

    1. A250
    2. B300
    3. C400
    4. D450

    Answer: (A) 250

    Explanation

    The 200-cycle serial portion cannot be sped up. The 800-cycle parallel portion divides across 16 processors, taking 800/16 = 50 cycles. The total is 200 + 50 = 250 cycles, so option A is correct.

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17. Question 17

    UGC NET August 2024

    Arrange the given steps required for a Direct
    Memory Access (DMA) transfer in the correct
    order.
    A. Initiate DMA transfer request
    B. Transfer data directly between peripheral and
    memory
    C. Processor grants DMA control over the
    system bus
    D. DMA controller completes data transfer and
    signals completion

    1. A(C), (A), (B), (D)
    2. B(A),(C),(B),(D)
    3. C(A), (B), (C), (D)
    4. D(C), (B), (A), (D)

    Answer: (B) (A),(C),(B),(D)

    Explanation

    A DMA transfer begins with the peripheral raising a transfer request (A). The processor then releases the bus and grants the controller DMA control (C). The controller moves data directly between peripheral and memory (B), and finally signals completion (D). That order is option B.

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18. Question 18

    UGC NET August 2024

    Match List-I with List-II.

    List-I (Recurrence Relation)	List-II (Complexity)
    (A) T(n) = 2T(n/2) + n	(I) T(n) = θ(n log n) {exact solution}
    (B) T(n) = T(n/2) + 1	(II) O(n²)
    (C) T(n) = 2T(n/2) + 1	(III) T(n) = θ(n) {exact solution}
    (D) T(n) = T(n−1) + n	(IV) O(n)

    1. A(A)-(I), (B)-(IV), (C)-(III), (D)-(II)
    2. B(A)-(IV), (B)-(II), (C)-(I), (D)-(III)
    3. C(A)-(I), (B)-(III), (C)-(IV), (D)-(II)
    4. D(A)-(III), (B)-(I), (C)-(IV), (D)-(II)

    Answer: (C) (A)-(I), (B)-(III), (C)-(IV), (D)-(II)

    Explanation

    By the Master Theorem, T(n) = 2T(n/2) + n is θ(n log n), so (A)-(I). T(n) = T(n−1) + n sums to θ(n²), so (D)-(II). T(n) = 2T(n/2) + 1 is θ(n), and T(n) = T(n/2) + 1 is θ(log n) — which is not listed, so the official key pairs (B) with the remaining O(n)-family entry. The official NTA key is option C. Note that (B) = T(n/2) + 1 is θ(log n), not θ(n): option A pairs the exact-θ(n) entry with (C) and is the mathematically tighter reading. Answer as per the official key.

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19. Question 19

    UGC NET August 2024

    A vector processor with 16 lanes can perform an
    operation on 1024 elements with each operation
    taking 5 clock cycles. How many cycles are
    needed to complete the operation?

    1. A64
    2. B80
    3. C100
    4. D128

    Answer: (A) 64

    Explanation

    With 16 lanes, 1024 elements are covered in 1024/16 = 64 passes through the vector pipeline, so option A is the official key. Note the wording: each pass is stated to take 5 clock cycles, so the number of cycles would be 64 × 5 = 320. The key counts operations rather than cycles.

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20. Question 20

    UGC NET December 2023

    Which of the following circuit is used to store one bit of data ?

    1. AEncoder
    2. BDecoder
    3. CFlip-Flop
    4. DRegister

    Answer: (C) Flip-Flop

    Explanation

    The key idea is stated in the problem: Which of the following circuit is used to store one bit of data ?. The correct answer is C: Flip-Flop. It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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21. Question 21

    UGC NET December 2023

    Identify the code sequence : 1010 1011 1001 1000

    1. ABCD
    2. BExcess-3
    3. CGray
    4. DExcess-3 gray

    Answer: (C) Gray

    Explanation

    The key idea is stated in the problem: Identify the code sequence : 1010 1011 1001 1000. The correct answer is C: Gray. It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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22. Question 22

    UGC NET December 2023

    The microoperation which divides a signed binary number by 2 is :

    1. ACircular shift
    2. BLogical shift
    3. CArithmetic shift right
    4. DArithmetic shift left

    Answer: (B) Logical shift

    Explanation

    The key idea is stated in the problem: The microoperation which divides a signed binary number by 2 is :. The correct answer is B: Logical shift. It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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23. Question 23

    UGC NET December 2023

    "CREATE TABLE T" in SQL is an example of : (14) Normalization

    1. ANormalization
    2. BDML
    3. CDDL
    4. DPrimary key

    Answer: (C) DDL

    Explanation

    The key idea is stated in the problem: "CREATE TABLE T" in SQL is an example of : (14) Normalization. The correct answer is C: DDL. It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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24. Question 24

    UGC NET December 2023

    An Address in main memory is called :

    1. AVirtual address
    2. BMemory address
    3. CLogical address
    4. DPhysical address

    Answer: (D) Physical address

    Explanation

    The key idea is stated in the problem: An Address in main memory is called :. The correct answer is D: Physical address. It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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25. Question 25

    UGC NET December 2023

    The average time required to search a storage location in memory and obtain its contents is called :

    1. AAccess time
    2. BLatency time
    3. CResponse time
    4. DReading time

    Answer: (A) Access time

    Explanation

    The key idea is stated in the problem: The average time required to search a storage location in memory and obtain its contents is called :. The correct answer is A: Access time. It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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26. Practise Computer System Architecture in a timed set

27. Question 26

    UGC NET December 2023

    If N2=NXN, Nis set of natural numbers and R is relation on N2, s.t. RC N2xN2i.e. <x,y> R<u,v> xv =yu, then which of the followings are TRUE ?
    A. Reflexive
    B. Symmetric
    C. Transitive
    D. Assymmetric Choose the correct answer from the options given below :

    1. AA and B only
    2. BB and C only
    3. CA, C and D only
    4. DA, B and C only

    Answer: (D) A, B and C only

    Explanation

    The key idea is stated in the problem: If N2=NXN, Nis set of natural numbers and R is relation on N2, s.t. RC N2xN2i.e. <x,y> R<u,v> xv =yu, then which of the followings are TRUE ?
    A. Reflexive
    B. Symmetric
    C. Transitive
    D. Assymmetric Choose the correct answer from the options given below :. The correct answer is D: A, B and C only. It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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28. Question 27

    UGC NET December 2023

    The interface(s) that provide(s) I/O transfer of data directly to and from the memory unit peripheral is/are termed as :
    A. DMA (Direct Memory Access)
    B. IOP (Input-Output Processor)
    C. Serial Interface
    D. Parallel Interface Choose the correct answer from the options given below :

    1. AA only
    2. BB only
    3. CA and B only
    4. DC and D only

    Answer: (C) A and B only

    Explanation

    The key idea is stated in the problem: The interface(s) that provide(s) I/O transfer of data directly to and from the memory unit peripheral is/are termed as :
    A. DMA (Direct Memory Access)
    B. IOP (Input-Output Processor)
    C. Serial Interface
    D. Parallel Interface Choose the correct answer from . The correct answer is C: A and B only. It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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29. Question 28

    UGC NET December 2023

    Which of the following statements is/are NOT CORRECT about NUMA ?
    A. LOAD and STORE instructions are used to access remote memory.
    B. There is a single address space visible to all CPU.
    C. Access to local memory is slower than access to remote memory.
    D. When the access time to remote memory is hidden, the system is called NC - NUM
    A.
    E. In CC- NUMA, Coherent caches are present. Choose the correct answer from the options given below :

    1. A(A) and (C) Only
    2. B(B) and (D) Only
    3. C(A) and (E) Only
    4. D(© and (D) Only

    Answer: (D) (© and (D) Only

    Explanation

    The key idea is stated in the problem: Which of the following statements is/are NOT CORRECT about NUMA ?
    A. LOAD and STORE instructions are used to access remote memory.
    B. There is a single address space visible to all CPU.
    C. Access to local memory is slower than access to remote memory.
    D. W. The correct answer is D: (© and (D) Only. It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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30. Question 29

    UGC NET December 2023

    Consider the following code segment : int arr [] = {0, 1, 2, 3, 4}; int i=1, *ptr; ptr=arr+2; arrange the following printf statements in the increasing order of their output.
    A. printf ("%d", pti);
    B. printf ("%d", ptr[i+1]);
    C. _ printf ("%d", ptr[—i));
    D. printf ("%d", ptr[—i+1]); Choose the correct answer from the options given below :

    1. A©, (A), 8), ©)
    2. B(©, (), (A), 8)
    3. C(D), (A), (8). ©
    4. D(A), @), (D), ©

    Answer: (B) (©, (), (A), 8)

    Explanation

    The key idea is stated in the problem: Consider the following code segment : int arr [] = {0, 1, 2, 3, 4}; int i=1, *ptr; ptr=arr+2; arrange the following printf statements in the increasing order of their output.
    A. printf ("%d", pti);
    B. printf ("%d", ptr[i+1]);
    C. _ printf ("%d", ptr[—i));
    D. The correct answer is B: (©, (), (A), 8). It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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31. Question 30

    UGC NET December 2023

    Match List-I with List-II.

    Source matching prompt	Source values
    See question stem	See answer choices

    1. A(A)-@), (BU), (©-AV), (D)-()
    2. B(A)-(), ()-@), (-CV), (D)-(N)
    3. C(A)-(D, (B)-(), ©-(, (Dav)
    4. D(A)-(V), (BW), ©-(), (D)-@)

    Answer: (B) (A)-(), ()-@), (-CV), (D)-(N)

    Explanation

    The key idea is stated in the problem: Match List - I with List - II. List - I List - II
    A. LRU (I) A page is written to secondary memory only when it has been selected for replacement
    B. Demand cleaning (II) A page that has not been referenced for the longest time is replaced
    C. Long term sched. The correct answer is B: (A)-(), ()-@), (-CV), (D)-(N). It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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32. Question 31

    UGC NET December 2023

    Match List-I with List-II.

    Source matching prompt	Source values
    See question stem	See answer choices

    1. A(A)-CV), BC, ()-@, (P)-()
    2. B(AC, B)-(), (CAV), (P)-(II)
    3. C(A)-
    4. D(A)-(V), (B)-(D, (C)-(0), (D)-)

    Answer: (B) (AC, B)-(), (CAV), (P)-(II)

    Explanation

    The key idea is stated in the problem: Match List - I with List - II according to input to the compiler phase that process it : List - I List - IT
    A. Syntax tree (I) Code generator
    B. Intermediate (II) Semantic analyzer representation
    C. Token stream (II) Lexical analyze
    D. Character stream (IV. The correct answer is B: (AC, B)-(), (CAV), (P)-(II). It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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33. Question 32

    UGC NET November 2020

    Consider a machine with byte-addressable main memory of 2¹⁶ bytes and block size 8 bytes. A direct-mapped cache has 32 lines. How many bits are in the tag, line, and word fields of a main-memory address?

    1. A8, 5, 3
    2. B8, 6, 2
    3. C7, 5, 4
    4. D7, 6, 3

    Answer: (A) 8, 5, 3

    Explanation

    A 2¹⁶-byte memory uses 16 address bits. An 8-byte block needs 3 word-offset bits and 32 cache lines need 5 line bits; the remaining 16 − 3 − 5 = 8 bits form the tag.

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34. Question 33

    UGC NET November 2020

    The following basic-computer program is stored in memory. What is the accumulator content after execution?

    210 CLA
    211 ADD 217
    212 INC
    213 STA 217
    214 LDA 218
    215 CMA
    216 AND 217
    217 1234H
    218 9CE2H

    1. A1002H
    2. B2011H
    3. C2022H
    4. D0215H

    Answer: (D) 0215H

    Explanation

    CLA clears AC; ADD 217 and INC produce 1235H, which STA stores at 217. LDA 218 loads 9CE2H, CMA gives 631DH, and 631DH AND 1235H equals 0215H.

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35. Question 34

    UGC NET November 2020

    A non-pipeline system takes 50 ns per task. The same task uses a six-segment pipeline with a 10 ns clock. Determine the approximate speedup for 500 tasks.

    1. A6
    2. B4.95
    3. C5.7
    4. D5.5

    Answer: (B) 4.95

    Explanation

    Non-pipelined time is 500 × 50 = 25,000 ns. Pipeline time is (6 + 500 − 1) × 10 = 5,050 ns, including fill time. The speedup is 25,000/5,050 ≈ 4.95. A speedup of 6 ignores pipeline fill and drain overhead.

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36. Question 35

    UGC NET November 2020

    For a k-segment pipeline, which statements are true?
    A. The theoretical maximum speed-up is k.
    B. A finite k-segment pipeline cannot attain that maximum exactly.
    C. All pipeline segments always take the same computation time.

    1. A(A) and (B) only
    2. B(B) and (C) only
    3. C(A) and (C) only
    4. D(A), (B), and (C)

    Answer: (A) (A) and (B) only

    Explanation

    With balanced stages and a long stream, speed-up approaches k, but fill and drain overhead prevent a finite workload from reaching it exactly. Equal stage times are an ideal design goal, not a universal property.

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37. Question 36

    UGC NET November 2020

    Which statements about a multiprocessor system are true?
    A. It is controlled by one operating system.
    B. It consists of multiple computers connected by communication lines.
    C. It is classified as an MIMD system.

    1. A(A) only
    2. B(A) and (B) only
    3. C(A) and (C) only
    4. D(B) and (C) only

    Answer: (C) (A) and (C) only

    Explanation

    A multiprocessor is a tightly coupled system managed by one OS and normally follows the MIMD model. Statement B instead describes a distributed system of separate computers.

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38. Question 37

    UGC NET November 2020

    Which cloud concept is related to pooling and sharing resources?
    A. Virtual memory
    B. Service
    C. Virtualization

    1. A(C) only
    2. B(A) and (B) only
    3. C(A) only
    4. D(B) only

    Answer: (A) (C) only

    Explanation

    Virtualization abstracts physical resources so they can be pooled and allocated to multiple users or services. Virtual memory and “service” are not the resource-pooling mechanism intended here.

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39. Question 38

    UGC NET November 2020

    Match List I with List II

    List I
    A. Handshaking
    B. Programmed I/O
    C. Interrupt-initiated I/O
    D. WO processor

    List IL

    V/O interface informs the CPU that
    device is ready for transfer

    requires two control signals working in
    opposite directions

    has local memory & control large set of
    I/O devices.

    require CPU to check the I/O flag &
    perform transfer

    List I	List II
    Items are listed in the question stem.	Match each item to its stated description or complexity.

    1. AOCR review required
    2. BOCR review required
    3. CA-II, B-IV, C-I, D-II
    4. DOCR review required

    Answer: (C) A-II, B-IV, C-I, D-II

    Explanation

    Handshaking uses opposite-direction control signals; programmed I/O polls the device flag; interrupt-driven I/O lets the interface notify the CPU; an I/O processor has local control and memory for many devices.

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40. Question 39

    UGC NET November 2020

    Arrange the following types of machine in descending order of complexity.
    A. SISD
    B. MIMD
    C. SIMD

    1. AOCR review required
    2. BOCR review required
    3. CB,C,A 4 CAB
    4. DOCR review required

    Answer: (C) B,C,A 4 CAB

    Explanation

    In Flynn’s taxonomy, MIMD is the most general and complex of the listed architectures, followed by SIMD and then SISD. Hence the descending order is B, C, A.

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41. Question 40

    UGC NET November 2020

    Given below are two statements:

    Statement I: Hardwired control unit can be optimized to produce fast mode of operation.
    Statement II: Indirect addressing mode needs two memory reference to fetch the operand.
    In the light of the above statements, choose the correct answer from the options given below
    (i) Both Statement I and Statement II are true

    1. AOCR review required
    2. BBoth Statement I and Statement II are false
    3. CStatement I is correct but Statement II is false
    4. DStatement I is incorrect but Statement II is true.

    Answer: (A) OCR review required

    Explanation

    Hardwired control uses fixed logic and can be optimised for speed. With indirect addressing, the instruction supplies an address whose memory contents provide the effective operand address, requiring an additional memory reference.

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